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target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Fri, 5 Mar 2021 13:03:51 +0000 (14:03 +0100)
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Sun, 14 Mar 2021 13:48:54 +0000 (14:48 +0100)
commit007479842b27e03173a333b8c2e0dae14be64f8d
tree675d81da6392aa9d0d51f41ba85ac96c4b56f7adtree | snapshot
parent9b620609d79ca0e101af024435c5b38b80478969commit | diff
target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2

if r3+1 and r2 are the same then we would overwrite r2 with our first
move and use the wrong result for the shift. Thus we store the result
from the mov in a temp.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
target/tricore/translate.c diff | blob | history
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