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(parent: 4859bfc) | patch
csky: Cache and TLB routines
authorGuo Ren <ren_guo@c-sky.com>
Wed, 5 Sep 2018 06:25:10 +0000 (14:25 +0800)
committerGuo Ren <ren_guo@c-sky.com>
Thu, 25 Oct 2018 15:36:19 +0000 (23:36 +0800)
commit00a9730e1007c6cc87a7c78af2f24a4105d616ee
treec014e5a0606a7a88b6e3493f49862c040f9aeea8tree | snapshot
parent4859bfca11c7d63d55175bcd85a75d6cee4b7184commit | diff
csky: Cache and TLB routines

This patch adds cache and tlb sync codes for abiv1 & abiv2.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
15 files changed:
arch/csky/abiv1/cacheflush.c [new file with mode: 0644] blob
arch/csky/abiv1/inc/abi/cacheflush.h [new file with mode: 0644] blob
arch/csky/abiv2/cacheflush.c [new file with mode: 0644] blob
arch/csky/abiv2/inc/abi/cacheflush.h [new file with mode: 0644] blob
arch/csky/include/asm/barrier.h [new file with mode: 0644] blob
arch/csky/include/asm/cache.h [new file with mode: 0644] blob
arch/csky/include/asm/cacheflush.h [new file with mode: 0644] blob
arch/csky/include/asm/io.h [new file with mode: 0644] blob
arch/csky/include/asm/tlb.h [new file with mode: 0644] blob
arch/csky/include/asm/tlbflush.h [new file with mode: 0644] blob
arch/csky/include/uapi/asm/cachectl.h [new file with mode: 0644] blob
arch/csky/mm/cachev1.c [new file with mode: 0644] blob
arch/csky/mm/cachev2.c [new file with mode: 0644] blob
arch/csky/mm/syscache.c [new file with mode: 0644] blob
arch/csky/mm/tlb.c [new file with mode: 0644] blob
ep93xx device tree rework repo: git://git.maquefel.me/linux.git