target/riscv: add support for zdinx
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 11 Feb 2022 04:39:18 +0000 (12:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 3 Mar 2022 03:14:50 +0000 (13:14 +1000)
commit026e73fa2665f07d24bb715f2c405c3e38587812
tree5173756a92ff82b875aa3e5c27e1f39fabbb09fd
parente1a29bbd5493634afd52f1724331728abdd196b8
target/riscv: add support for zdinx

  -- update extension check REQUIRE_ZDINX_OR_D
  -- update double float point register read/write

Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvd.c.inc
target/riscv/translate.c