clk: mediatek: Export PLL operations symbols
authorJohnson Wang <johnson.wang@mediatek.com>
Mon, 21 Nov 2022 12:29:54 +0000 (20:29 +0800)
committerChen-Yu Tsai <wenst@chromium.org>
Tue, 29 Nov 2022 06:43:07 +0000 (14:43 +0800)
commit029c936ae7e14ce49d043527087abb5f4b0ea48c
tree5216fb9f22f8cf989709c384729b60b5844aa773
parent3256ea4f6582d2cb9b63ad96451957c217a52582
clk: mediatek: Export PLL operations symbols

Export PLL operations and register functions for different type
of clock driver used.

Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221121122957.21611-2-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
drivers/clk/mediatek/clk-pll.c
drivers/clk/mediatek/clk-pll.h