ARM: dts: qcom: sdx65: Add support for A7 PLL clock
authorRohit Agarwal <quic_rohiagar@quicinc.com>
Tue, 22 Feb 2022 04:56:23 +0000 (10:26 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Wed, 13 Apr 2022 02:22:26 +0000 (21:22 -0500)
commit02c5553523c6cfdab4335ab26ff65f679c7c91ac
treef9bee50becb3c19c8ddf555fa729a1fe83dda8f3
parentc20aa951ee14fe0dfa2beed19aaee1fd33d50a6e
ARM: dts: qcom: sdx65: Add support for A7 PLL clock

On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
arch/arm/boot/dts/qcom-sdx65.dtsi