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(parent: 5e03b6d) | patch
target/i386: correctly mask SSE4a bit indices in register operands
authorPaolo Bonzini <pbonzini@redhat.com>
Sun, 18 Sep 2022 07:15:22 +0000 (09:15 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Mon, 19 Sep 2022 13:16:00 +0000 (15:16 +0200)
commit034668c329bb3e257a1f259571bd462938522e7a
tree99a0cfd65941b4e30de004982ba14d46f8a90875tree | snapshot
parent5e03b6daf66dfb0f5512a0dfc9e21e749b6f67b7commit | diff
target/i386: correctly mask SSE4a bit indices in register operands

SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be
immediates or taken from an XMM register.  In both cases, the fields are
6-bit wide and the top two bits in the byte are ignored.  translate.c is
doing that correctly for the immediate case, but not for the XMM case, so
fix it.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/ops_sse.h diff | blob | history
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