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riscv: sifive_u: Update the plic hart config to support multicore
authorBin Meng <bmeng.cn@gmail.com>
Fri, 17 May 2019 15:51:25 +0000 (08:51 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Thu, 27 Jun 2019 09:47:06 +0000 (02:47 -0700)
commit05446f4133ea1fe4b444ba80a823fc1df1a9eeaf
tree85484054e09d6852807df498a18852536528f56ftree | snapshot
parent382cb4392ff8c3fa911d10da959eb8b0cbee15afcommit | diff
riscv: sifive_u: Update the plic hart config to support multicore

At present the PLIC is instantiated to support only one hart, while
the machine allows at most 4 harts to be created. When more than 1
hart is configured, PLIC needs to instantiated to support multicore,
otherwise an SMP OS does not work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
hw/riscv/sifive_u.c diff | blob | history
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