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MN10300: Don't hard code the cacheline size in register defs
authorAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Wed, 27 Oct 2010 16:28:39 +0000 (17:28 +0100)
committerDavid Howells <dhowells@redhat.com>
Wed, 27 Oct 2010 16:28:39 +0000 (17:28 +0100)
commit06019be31a1b5812eec5bb3e1dbdeced04950e8e
treec885748da5ba7232877cb509ba59d5c0aa1bc43atree | snapshot
parenta116956423e1cdc4398110bdc66d66ae4c5ba90fcommit | diff
MN10300: Don't hard code the cacheline size in register defs

Don't hard code the cacheline size in the cache control register definitions.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
arch/mn10300/include/asm/cache.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git