tools/power/x86/intel-speed-select: Read TRL from mailbox
authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Tue, 24 Nov 2020 00:56:05 +0000 (16:56 -0800)
committerHans de Goede <hdegoede@redhat.com>
Tue, 8 Dec 2020 10:12:15 +0000 (11:12 +0100)
commit07f262d80d5f1f426da4557066bf0ec24ee32d97
tree41a93de4b1d10054ae5e66120b237d5001845edb
parentdea5b80a043f6cd6ad341d9957a43e363366630e
tools/power/x86/intel-speed-select: Read TRL from mailbox

When SST-PP feature is not present, the TRL (Turbo Ratio Limits)
is read from MSRs. This is done as the mailbox command will fail
on Skylake-X based platform. But for IceLake servers, mailbox
commands can still be used. So add a check to allow for non Skylake
based platforms to read from mail box commands.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://lore.kernel.org/platform-driver-x86/57d6648282491906e0e1f70fe3b9a44f72cec90d.camel@intel.com/
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
tools/power/x86/intel-speed-select/isst-core.c
tools/power/x86/intel-speed-select/isst.h