disas/riscv.c: rvv: Add disas support for vector instructions
authorYang Liu <liuyang22@iscas.ac.cn>
Wed, 28 Sep 2022 05:18:42 +0000 (13:18 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 14 Oct 2022 04:29:50 +0000 (14:29 +1000)
commit07f4964d1785e9c230282074a5aef1eb7368d378
treee05660d0b74f702f3d2d495c6bb206fa93cb06a8
parenta5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0
disas/riscv.c: rvv: Add disas support for vector instructions

Tested with https://github.com/ksco/rvv-decoder-tests

Expected checkpatch errors for consistency and brevity reasons:

ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
disas/riscv.c