hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
authorPeter Maydell <peter.maydell@linaro.org>
Tue, 2 Aug 2022 13:19:25 +0000 (14:19 +0100)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Mon, 8 Aug 2022 21:43:11 +0000 (23:43 +0200)
commit09d12c81ec5d8dc9208e5739d17a56c34be96247
treed40a96be4fe7863778f654666e3aae2bd5c979f1
parentbd64c210ce2bebba993ee49d34327706ec47f685
hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses

In real hardware, the APB and AHB PNP data tables can be accessed
with byte and halfword reads as well as word reads.  Our
implementation currently only handles word reads.  Add support for
the 8 and 16 bit accesses.  Note that we only need to handle aligned
accesses -- unaligned accesses should continue to trap, as happens on
hardware.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Message-Id: <20220802131925.3380923-1-peter.maydell@linaro.org>
Tested-by: Tomasz Martyniak <gitlab.com/tom4r>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
hw/misc/grlib_ahb_apb_pnp.c
hw/misc/trace-events