drm/amd/display: Write flip addr to scratch reg for subvp
authorAlvin Lee <alvin.lee2@amd.com>
Thu, 10 Aug 2023 15:50:52 +0000 (11:50 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 30 Aug 2023 18:59:14 +0000 (14:59 -0400)
commit0b9dc439f4046ef9e43f54989f6c3ff6cddc6d1b
tree0097a2d4ffa00fc469b78031cb49856593ac84c3
parentec4247823bbc88a7ee81fec579d1b4408bba686d
drm/amd/display: Write flip addr to scratch reg for subvp

[Description]
SubVP needs to "calculate" the earliest in use META address
by using the current primary / meta addresses, but this leads
to a race condition where FW and driver can read/write the
address at the same time and intermittently produce inconsistent
address offsets. To mitigate this issue without locking (too slow),
save each surface flip addr into scratch registers and use this
to keep track of the earliest in use META addres.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/display/dc/inc/core_types.h
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c