drm/i915: Carve up struct intel_dpll_hw_state
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 12 Apr 2024 18:27:01 +0000 (21:27 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 17 Apr 2024 14:02:24 +0000 (17:02 +0300)
commit0bfdd6da01b2bf43edfce73df6ad80da5a8b3425
treed4dae4a2091623329b0e2c3d8be4753da8c537a6
parente8ba9204db041776d8e3b7eb396160a6967911c8
drm/i915: Carve up struct intel_dpll_hw_state

struct intel_dpll_hw_state has a spot for all possible
PLL registers across all platforms (well, apart from
cx0/snps). This makes it rather confusing when trying to
figure out which members belong to which platform(s).

Split the struct up into five different platform specific
sub-structures. For now this will actually increase the size
a little bit as we have to duplicate a few members from
skl to icl, but that will be remedied soon when we turn
the thing into a union.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412182703.19916-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_dpll.c
drivers/gpu/drm/i915/display/intel_dpll.h
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
drivers/gpu/drm/i915/display/intel_pch_display.c