target/riscv: Define macros and variables for ss1p13
authorFea.Wang <fea.wang@sifive.com>
Thu, 6 Jun 2024 13:54:50 +0000 (21:54 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 12:52:24 +0000 (22:52 +1000)
commit0c2d5f7396d73a957ba665d7824c9ee7926c0357
tree00a0c380e5430bf7422c68c1bbda3f2ce301d092
parenta1a8e7768f321232cff276817adf37e116ba8423
target/riscv: Define macros and variables for ss1p13

Add macros and variables for RISC-V privilege 1.13 support.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-3-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_cfg.h