target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
authorAlvin Chang <alvinga@andestech.com>
Tue, 19 Dec 2023 12:32:44 +0000 (20:32 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 9 Feb 2024 10:40:32 +0000 (20:40 +1000)
commit0c4e579aac30abd26818ebaec8e1b633eb9f3952
treec6bd791a8f63b2c5739179b15f21d20a7478a424
parent10efbe01ce40845aa2324d2abecd6664c7d8bf1c
target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/csr.c
target/riscv/debug.c