RISC-V: KVM: Implement perf support without sampling
authorAtish Patra <atishp@rivosinc.com>
Tue, 7 Feb 2023 12:14:28 +0000 (17:44 +0530)
committerAnup Patel <anup@brainfault.org>
Tue, 7 Feb 2023 15:06:03 +0000 (20:36 +0530)
commit0cb74b65d2e5e6ec3ed60c8890014b1bcd0c81c9
tree239051785bd6103602817a1319ba855e7c54f209
parenta9ac6c37521ff3f81eba7fada8773c362652d75f
RISC-V: KVM: Implement perf support without sampling

RISC-V SBI PMU & Sscofpmf ISA extension allows supporting perf in
the virtualization enviornment as well. KVM implementation
relies on SBI PMU extension for the most part while trapping
& emulating the CSRs read for counter access.

This patch doesn't have the event sampling support yet.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/vcpu_pmu.c