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(parent: c4e1f0b) | patch
aspeed/smc: Add DMA calibration settings
authorCédric Le Goater <clg@kaod.org>
Wed, 4 Sep 2019 07:05:02 +0000 (09:05 +0200)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 13 Sep 2019 15:05:01 +0000 (16:05 +0100)
commit0d72c717029f59fa0531fee419734ad7f14b1331
tree608c9267ddb37dfa24eef77d88d1531c059cd2a2tree | snapshot
parentc4e1f0b48322a9bc98c37f8413553cb6131daafecommit | diff
aspeed/smc: Add DMA calibration settings

When doing calibration, the SPI clock rate in the CE0 Control Register
and the read delay cycles in the Read Timing Compensation Register are
set using bit[11:4] of the DMA Control Register.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190904070506.1052-7-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/ssi/aspeed_smc.c diff | blob | history
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