riscv: add ISA extension parsing for scalar crypto
authorEvan Green <evan@rivosinc.com>
Tue, 14 Nov 2023 14:12:39 +0000 (09:12 -0500)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 12 Dec 2023 23:45:00 +0000 (15:45 -0800)
commit0d8295ed975b6df487f0b4018770a60b070fc76d
treec05525e4722520eb5238ba2d9525dd7b6cca954e
parentbe6bef2acb75ca980671de19d406c0310d646d2b
riscv: add ISA extension parsing for scalar crypto

The Scalar Crypto specification defines Zk as a shorthand for the
Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk,
which are all shorthands for various other extensions. The detailed
breakdown can be found in their dt-binding entries.

Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing
"zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt.
For example, setting the "riscv,isa" DT property to "rv64imafdc_zk"
should generate the following cpuinfo output:
"rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zkt"

riscv_isa_ext_data grows a pair of new members, to permit setting the
relevant bits for "bundled" extensions, both while parsing the ISA string
and the new dedicated extension properties.

Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Evan Green <evan@rivosinc.com>
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231114141256.126749-4-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/cpufeature.h
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpufeature.c