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(parent: 15732b8) | patch
target/riscv: Expose interrupt pending bits as GPIO lines
authorAlistair Francis <alistair.francis@wdc.com>
Mon, 30 Aug 2021 05:34:20 +0000 (15:34 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Sep 2021 21:56:49 +0000 (07:56 +1000)
commit0f0b70eeecdd4e0f29efe28a7ffec01cbe5c43bf
treed375b12954a4b939bc8a135790b7450b7a56d9ebtree | snapshot
parent15732b8ed290460334ee58dd25939da733f362fdcommit | diff
target/riscv: Expose interrupt pending bits as GPIO lines

Expose the 12 interrupt pending bits in MIP as GPIO lines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
target/riscv/cpu.c diff | blob | history
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