gpio: pmic-eic-sprd: Configure the bit corresponding to the EIC through offset
authorWenhua Lin <Wenhua.Lin@unisoc.com>
Tue, 2 Jan 2024 08:28:29 +0000 (16:28 +0800)
committerBartosz Golaszewski <bartosz.golaszewski@linaro.org>
Wed, 3 Jan 2024 08:50:47 +0000 (09:50 +0100)
commit0f57b21300c8c7d3500de995ab3018cc7ec41249
tree152139cfc9c51dcfb2a574f1989e82ecd7a6e431
parentf34fd6ee1be84c6e64574e9eb58f89d32c7f98a4
gpio: pmic-eic-sprd: Configure the bit corresponding to the EIC through offset

A bank PMIC EIC contains 16 EICs, and the operating registers
are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
will cause the configuration of other EICs to be affected when
operating a certain EIC. In order to solve this problem, configure
the bit corresponding to the EIC through offset.

Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
drivers/gpio/gpio-pmic-eic-sprd.c