target/arm: Implement HCR_EL2.TTLBIS traps
authorPeter Maydell <peter.maydell@linaro.org>
Wed, 14 Dec 2022 14:27:08 +0000 (14:27 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 15 Dec 2022 11:18:20 +0000 (11:18 +0000)
commit0f66d223e3b688a93ae02dc114d2891bbb0e09cc
tree5d69ce41481efd0875cece049433a96fec1f2794
parentd2fd931362a693d988e3204ddc8068875dcf8fab
target/arm: Implement HCR_EL2.TTLBIS traps

For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
TLB maintenance instructions that operate on the inner shareable
domain:

AArch64:
 TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
 TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
 TLBI RVALE1IS, and TLBI RVAALE1IS.

AArch32:
 TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
 and TLBIMVAALIS.

Add the trapping support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
target/arm/helper.c