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(parent: dc9cd4e) | patch
tcg/riscv: Implement vector sat/mul ops
authorTANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Mon, 7 Oct 2024 02:56:56 +0000 (10:56 +0800)
committerRichard Henderson <richard.henderson@linaro.org>
Tue, 22 Oct 2024 18:57:25 +0000 (11:57 -0700)
commit101c1ef56221926718eb70d33ac2844d139d55e0
treee7fcf5b84d89b09465a60b3cb87bbab9f33047d7tree | snapshot
parentdc9cd4ec12074a762ca9f41a822a27aa702284d4commit | diff
tcg/riscv: Implement vector sat/mul ops

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-9-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tcg/riscv/tcg-target.c.inc diff | blob | history
tcg/riscv/tcg-target.h diff | blob | history
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