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(parent: 13b5ae9) | patch
aspeed/soc: support ADC for AST2700
authorJamin Lin <jamin_lin@aspeedtech.com>
Thu, 18 Jul 2024 06:49:12 +0000 (14:49 +0800)
committerCédric Le Goater <clg@redhat.com>
Sun, 21 Jul 2024 05:46:38 +0000 (07:46 +0200)
commit11bea810f7c1215e36824ed291a64e8f4e6f28df
treef30bc59dd336e55f346748f467aa5b457e7a8f3ctree | snapshot
parent13b5ae94ed4d03d4992af867d0edb075651a4da9commit | diff
aspeed/soc: support ADC for AST2700

Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_0000 and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
hw/arm/aspeed_ast27x0.c diff | blob | history
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