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RISC-V: Probe Svinval extension form ISA string
authorMayuresh Chitale <mchitale@ventanamicro.com>
Sun, 2 Oct 2022 04:48:31 +0000 (10:18 +0530)
committerAnup Patel <anup@brainfault.org>
Sun, 2 Oct 2022 04:48:31 +0000 (10:18 +0530)
commit122979aa26cd4a314aae889a0496eb829d50bc9e
treeeca6ea9de9f583ef7dc6556491b4191e339aa648tree | snapshot
parentd837f19195e77f7c89b6645c8311f5ea6ff67905commit | diff
RISC-V: Probe Svinval extension form ISA string

Just like other ISA extensions, we allow callers/users to detect the
presence of Svinval extension from ISA string.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/hwcap.h diff | blob | history
arch/riscv/kernel/cpu.c diff | blob | history
arch/riscv/kernel/cpufeature.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git