target/riscv: Reset henvcfg to zero
authorAndrew Jones <ajones@ventanamicro.com>
Thu, 15 Feb 2024 22:39:53 +0000 (19:39 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 8 Mar 2024 06:32:44 +0000 (16:32 +1000)
commit148189ff1313e995a0a84957c496ff92965151a2
tree7ce06b7b152f547420897f625d3da4822e6da7b4
parenta0952c15556d740a8dae88c7038ad5efe68745bc
target/riscv: Reset henvcfg to zero

The hypervisor should decide what it wants to enable. Zero all
configuration enable bits on reset.

Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
svadu extension") missed one reference to 'hade'. Change it now.

Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/csr.c