target/riscv: Don't adjust vscause for exceptions
authorAlistair Francis <alistair23@gmail.com>
Mon, 8 Jan 2024 00:13:27 +0000 (10:13 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 10 Jan 2024 08:47:47 +0000 (18:47 +1000)
commit1525d8aa3a56610e1c72f5dd305ec86ebad41769
tree4a2203e04ebb50a41be818b8ebbc0c57968130b1
parent9a7c6da4cd8458c76f619d84542f91d308ecb15f
target/riscv: Don't adjust vscause for exceptions

We have been incorrectly adjusting both the interrupt and exception
cause when using the hypervisor extension and trapping to VS-mode. This
patch changes the conditional to ensure we only adjust the cause for
interrupts and not exceptions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1708
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c