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(parent: c193304) | patch
hw/dma/pl080: Correct bug in register address decode logic
authorPeter Maydell <peter.maydell@linaro.org>
Mon, 20 Aug 2018 10:24:33 +0000 (11:24 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 20 Aug 2018 10:24:33 +0000 (11:24 +0100)
commit156448ab640baaeca185787eb303fe4d63edca26
treeffcfdd37ce22d96062f5e83c7f449d2cec6af97ctree | snapshot
parentc193304d4f9ef21c51ff412f6279ad459eedd438commit | diff
hw/dma/pl080: Correct bug in register address decode logic

A bug in the handling of the register address decode logic
for the PL08x meant that we were incorrectly treating
accesses to the DMA channel registers (DMACCxSrcAddr,
DMACCxDestaddr, DMACCxLLI, DMACCxControl, DMACCxConfiguration)
as bad offsets. Fix this long-standing bug.

Fixes: https://bugs.launchpad.net/qemu/+bug/1637974
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
hw/dma/pl080.c diff | blob | history
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