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arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
authorAlex Bennée <alex.bennee@linaro.org>
Thu, 1 Mar 2018 11:05:54 +0000 (11:05 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 1 Mar 2018 11:13:59 +0000 (11:13 +0000)
commit15f8a233c8c023dbc77b6fe6cd7c79eac9bee263
treec3f875320580048818c2a3263a8c1f8d500dc861tree | snapshot
parent931931904cb56b9310a1a9c7f88adfce7d9bd82bcommit | diff
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-22-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c diff | blob | history
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