clk: renesas: r9a07g044: Add OSTM clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 10 Nov 2021 08:20:19 +0000 (08:20 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 Nov 2021 09:47:18 +0000 (10:47 +0100)
commit161450134ae9bab3778c5f5732941162626d0eaa
tree917ee5f5ecdeaa3c9f8e76d876d0bd0f8201b37b
parentdc446cba4301bbe2dbe16711091635d987626410
clk: renesas: r9a07g044: Add OSTM clock and reset entries

Add OSTM{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c