drm/i915: Implement transcoder LRR for TGL+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 15 Sep 2023 10:38:00 +0000 (13:38 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 20 Sep 2023 19:32:55 +0000 (22:32 +0300)
commit16a9359401edcbc0a3814b9e3bc35cd478b34a3d
tree8248b10e05ae0ca0028bfa8d35235c099162a774
parent26f03ef816632945bec135f12a7f902b2de3a0c3
drm/i915: Implement transcoder LRR for TGL+

Implement low refresh rate (LRR) where we change the vblank
length by hand as requested, but otherwise keep the timing
generator running in non-VRR mode (ie. fixed refresh rate).

The panel itself must support VRR for this to work, and
only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
we need to make the switch properly. The double buffer
latching happens at the start of transcoders undelayed
vblank. The other thing that we change is
TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
that in DP mode. But I decided to keep writing it anyway
just to avoid more special cases in readout/state check.

v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
    the hardware
v3: Reconcile with VRR fastset
    Adjust update_lrr flag behaviour
    Make sure timings stay within VRR range
v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi)
    Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi)

TODO: Hook LRR into the automatic DRRS downclocking stuff?

Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230915103800.14218-1-ville.syrjala@linux.intel.com
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
drivers/gpu/drm/i915/display/intel_atomic.c
drivers/gpu/drm/i915/display/intel_crtc.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_device.h
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_vrr.c