target/riscv: Reassign instructions to the Zbb-extension
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Sat, 11 Sep 2021 14:00:10 +0000 (16:00 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 6 Oct 2021 22:33:21 +0000 (08:33 +1000)
commit16c38f36f5cb42bbfe7b9cd4bb29206a3ecab760
treecdef799e29bba360ed87b07718fa0852e9788d9f
parentfd4b81a304a5d50e719019d22eacca2d8ef4de69
target/riscv: Reassign instructions to the Zbb-extension

This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvb.c.inc