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(parent: 27f61d1) | patch
ppc/pnv: Implement Power9 CPU core thread state indirect register
authorNicholas Piggin <npiggin@gmail.com>
Thu, 11 Jul 2024 08:31:35 +0000 (18:31 +1000)
committerNicholas Piggin <npiggin@gmail.com>
Thu, 25 Jul 2024 23:21:06 +0000 (09:21 +1000)
commit16ffcb3401ddb991ec746de05595ba62eae45a1b
tree2ecaa5ebb4886572c2efa7ffbd05f7ca802d09d3tree | snapshot
parent27f61d1b0b708b4659894cd0677f65ebed6eaa0bcommit | diff
ppc/pnv: Implement Power9 CPU core thread state indirect register

Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
target/ppc/misc_helper.c diff | blob | history
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