target/riscv: Add MISA extension implied rules
authorFrank Chang <frank.chang@sifive.com>
Tue, 25 Jun 2024 11:46:26 +0000 (19:46 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 13:09:12 +0000 (23:09 +1000)
commit171773391a2b3a9d8aa4d807b945e9fabe080df6
treed7badcace38bdfc657efb7d76562b1daea9c06cf
parent047da861f94e1306cc1d76f3f76462e4f7ed2930
target/riscv: Add MISA extension implied rules

Add MISA extension implied rules to enable the implied extensions
of MISA recursively.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240625114629.27793-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c