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(parent: e0b7a79) | patch
clk: pistachio: Add sanity checks on PLL configuration
authorKevin Cernekee <cernekee@chromium.org>
Tue, 26 May 2015 22:01:09 +0000 (19:01 -0300)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 4 Jun 2015 19:43:39 +0000 (12:43 -0700)
commit17bfa3f7b3cd07e92b41ce7b5bea2dd8c8e2a8c3
treec24c733c8b2d1eaffb88bfdcc2054669e73af989tree | snapshot
parente0b7a79524771ad368abefbbcbd73f130f8e500ecommit | diff
clk: pistachio: Add sanity checks on PLL configuration

When setting the PLL rates, check that:

 - VCO is within range
 - PFD is within range
 - PLL is disabled when postdiv is changed
 - postdiv2 <= postdiv1

Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/pistachio/clk-pll.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git