drm/amd/display: To adjust dprefclk by down spread percentage
authorMartin Tsai <martin.tsai@amd.com>
Mon, 18 Dec 2023 08:36:44 +0000 (16:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 9 Jan 2024 20:43:53 +0000 (15:43 -0500)
commit17e74e11ac2b46e7514705ae7abfb93ac0e20bd6
tree6c81731cfea6c3a5c4706bdb5143c6dc79b9eed0
parent47bf0f83fc86df1bf42b385a91aadb910137c5c9
drm/amd/display: To adjust dprefclk by down spread percentage

[Why]
Panels show corruption with high refresh rate timings when ssc is
enabled.

[How]
Read down-spread percentage from lut to adjust dprefclk. Issues come
from S0i3 with this commit has been fixed by SMU.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
drivers/gpu/drm/amd/display/include/audio_types.h