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target/arm: Honor the HCR_EL2.TSW bit
authorRichard Henderson <richard.henderson@linaro.org>
Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)
commit1803d2713b29d85031cc964d545036bda9880f26
tree0625c10eef2377cf19c2432a0dcc1a2074cf9a7etree | snapshot
parent84929218512c19ec9a296fbfd7b39219e0c592aecommit | diff
target/arm: Honor the HCR_EL2.TSW bit

These bits trap EL1 access to set/way cache maintenance insns.

Buglink: https://bugs.launchpad.net/bugs/1863685
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper.c diff | blob | history
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