clk: sprd: add gate for pll clocks
authorXiaolong Zhang <xiaolong.zhang@unisoc.com>
Wed, 4 Mar 2020 07:27:24 +0000 (15:27 +0800)
committerStephen Boyd <sboyd@kernel.org>
Wed, 25 Mar 2020 02:03:56 +0000 (19:03 -0700)
commit187e5cd2d133771e978e7e4ea6aa684dfd1ce6ab
treecb09afa67e7e7b1743cd51b76cedad563fc59713
parentbb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
clk: sprd: add gate for pll clocks

Some sprd's gate clocks are used to the switch of pll, which
need to wait a certain time for stable after being enabled.

Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/sprd/gate.c
drivers/clk/sprd/gate.h