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(parent: b09c146) | patch
perf/x86/msr: Add missing CPU IDs
authorKan Liang <Kan.liang@intel.com>
Fri, 8 Sep 2017 21:34:48 +0000 (17:34 -0400)
committerThomas Gleixner <tglx@linutronix.de>
Mon, 25 Sep 2017 07:36:17 +0000 (09:36 +0200)
commit1aaccc40a1864053da26605b0297be16dd52641e
treef9611311989f8dfd59233db64a191cdb9e724592tree | snapshot
parentb09c146f8f63c0e03adba74df76bf9c2be466feccommit | diff
perf/x86/msr: Add missing CPU IDs

Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.

Signed-off-by: Kan Liang <Kan.liang@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ak@linux.intel.com
Cc: peterz@infradead.org
Cc: piotr.luc@intel.com
Cc: harry.pan@intel.com
Cc: srinivas.pandruvada@linux.intel.com
Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com
arch/x86/events/msr.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git