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(parent: a31cf51) | patch
clk: renesas: rcar-gen3: Add SDnH clock
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 10 Nov 2021 19:15:51 +0000 (20:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 19 Nov 2021 10:27:58 +0000 (11:27 +0100)
commit1abd04480866cead7b4129bd03246315b4575334
tree077d4a5076fd6fb3a6742ebcd5b55d18b587a2e3tree | snapshot
parenta31cf51bf6b4bf78ccb1c9fb40ea6231cf3df433commit | diff
clk: renesas: rcar-gen3: Add SDnH clock

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a774a1-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a774b1-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a774c0-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a774e1-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a7795-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a7796-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a77965-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a77980-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a77990-cpg-mssr.c diff | blob | history
drivers/clk/renesas/r8a77995-cpg-mssr.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git