net/mlx5: Fix MTMP register capability offset in MCAM register
authorGal Pressman <gal@nvidia.com>
Wed, 22 May 2024 19:26:54 +0000 (22:26 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 24 May 2024 12:27:07 +0000 (13:27 +0100)
commit1b9f86c6d53245dab087f1b2c05727b5982142ff
tree3b144c57e5285d4a22ef8cb287651da3fcb04d51
parentfca3b4791850b7e2181f0b3195b66d53df83151b
net/mlx5: Fix MTMP register capability offset in MCAM register

The MTMP register (0x900a) capability offset is off-by-one, move it to
the right place.

Fixes: 1f507e80c700 ("net/mlx5: Expose NIC temperature via hardware monitoring kernel API")
Signed-off-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
include/linux/mlx5/mlx5_ifc.h