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(parent: 1b929c0) | patch
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
authorEmil Renner Berthing <kernel@esmil.dk>
Tue, 20 Dec 2022 01:12:44 +0000 (09:12 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Mon, 26 Dec 2022 22:50:15 +0000 (22:50 +0000)
commit1caf002efa223f930ba508159535cf82ad4b2811
treea84ab0659337c0d740e9a724d2f9ba647e5dfda2tree | snapshot
parent1b929c02afd37871d5afb9d498426f83432e71c2commit | diff
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC

This cache controller is also used on the StarFive JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git