arm64: zynqmp: Set qspi tx-buswidth to 4
authorAmit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Mon, 22 May 2023 14:59:50 +0000 (16:59 +0200)
committerMichal Simek <michal.simek@amd.com>
Mon, 5 Jun 2023 11:15:02 +0000 (13:15 +0200)
commit1d831cade71883d0578e9f41d19d09b67f8263ac
treef5df520be2ca1b86cf26e5825bbd72834ddade39
parentf8673fd5700257576b23e0f6de71c153bac23978
arm64: zynqmp: Set qspi tx-buswidth to 4

All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller is capable of handling 1-4-4 write commands, so updated
the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the
tx data will be transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts