RISC-V: Fix missing break statement in disassembler
authorMichael Clark <mjc@sifive.com>
Sun, 29 Apr 2018 23:06:31 +0000 (11:06 +1200)
committerMichael Clark <mjc@sifive.com>
Sat, 5 May 2018 22:39:38 +0000 (10:39 +1200)
commit1dc34be1c90b2d3006078d9d331e53a849cdecf3
tree7011d38f076ea00bb3ed9ec2fc711f03d953d1c1
parent6296a799b14142ccb813b678227ae9e6bf0ffa79
RISC-V: Fix missing break statement in disassembler

This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
disas/riscv.c