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arm64: dts: renesas: r8a779h0: Add L3 cache controller
authorDuy Nguyen <duy.nguyen.rh@renesas.com>
Thu, 1 Feb 2024 14:19:16 +0000 (15:19 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 22 Feb 2024 10:03:32 +0000 (11:03 +0100)
commit20a942d60b34719df8a145e0364e90981380aefb
tree9ac595edb85f206cd857897bd21cc123df822504tree | snapshot
parent93e28f88710b2cbe51d6fe760cdf53fc9621f33ccommit | diff
arm64: dts: renesas: r8a779h0: Add L3 cache controller

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/r8a779h0.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git