drm/i915/mtl: Modify CAGF functions for MTL
authorBadal Nilawar <badal.nilawar@intel.com>
Mon, 14 Nov 2022 12:33:46 +0000 (18:03 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 17 Nov 2022 15:46:37 +0000 (10:46 -0500)
commit22009b6dad6621893e9b5c14665f247b6162499c
tree18c231fc38f2291222346c3ab6fc833d22c89357
parent01b8c2e60e96ce8a30d23683fba56b478be7287c
drm/i915/mtl: Modify CAGF functions for MTL

Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.

v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
    Move MTL branches in cagf functions to top (MattR)
    Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
    returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)

Bspec: 66300

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-4-badal.nilawar@intel.com
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gt/intel_rps.c