target/riscv: Add infrastructure for 'B' MISA extension
authorRob Bradford <rbradford@rivosinc.com>
Thu, 11 Jan 2024 16:16:43 +0000 (16:16 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 9 Feb 2024 00:39:16 +0000 (10:39 +1000)
commit2317ba9fa7f39402fec17847afe11b99e361d9a0
tree31dda0230fdcf91ad714d75bde33bae96caab5c1
parent878502e5fe58b7061a631275c1db9fa4f1442479
target/riscv: Add infrastructure for 'B' MISA extension

Add the infrastructure for the 'B' extension which is the union of the
Zba, Zbb and Zbs instructions.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240111161644.33630-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/tcg/tcg-cpu.c