clk: renesas: r9a09g011: Add eth clock and reset entries

clk: renesas: r9a09g011: Add eth clock and reset entries

Add ethernet clock/reset entries to CPG driver.

Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>