drm/i915/hdmi: C20 computed PLL frequencies
authorClint Taylor <clinton.a.taylor@intel.com>
Mon, 15 May 2023 23:17:25 +0000 (16:17 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 19 May 2023 17:11:57 +0000 (10:11 -0700)
commit234fcb978f61f53bc05c276f6204332fde2b4951
tree1830fd2ce5ebc5b51a8ac47e532f6122c4ca1e21
parentcb7b04c83e9006c39af6d806761fc628573920e8
drm/i915/hdmi: C20 computed PLL frequencies

Use algorithm to generate HDMI C20 PLL clock frequencies.

v2: checkpatch fixes

BSPEC: 64568
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
[mattrope: Wrapped one overly long line]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230515231725.3815199-3-clinton.a.taylor@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h