RISC-V: KVM: Make SBI uapi consistent with ISA uapi
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 13 Dec 2023 17:09:55 +0000 (18:09 +0100)
committerAnup Patel <anup@brainfault.org>
Fri, 29 Dec 2023 07:01:44 +0000 (12:31 +0530)
commit23e1dc45022eb65529aa30b1851a8d21a639c8f5
tree8818e02c12a9afff71dae224803a9f37ce88ea62
parent7602730d7f18ad9738d8fc5e5fd7f52a11fee399
RISC-V: KVM: Make SBI uapi consistent with ISA uapi

When an SBI extension cannot be enabled, that's a distinct state vs.
enabled and disabled. Modify enum kvm_riscv_sbi_ext_status to
accommodate it, which allows KVM userspace to tell the difference
in state too, as the SBI extension register will disappear when it
cannot be enabled, i.e. accesses to it return ENOENT. get-reg-list is
updated as well to only add SBI extension registers to the list which
may be enabled. Returning ENOENT for SBI extension registers which
cannot be enabled makes them consistent with ISA extension registers.
Any SBI extensions which were enabled by default are still enabled by
default, if they can be enabled at all.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_vcpu_sbi.h
arch/riscv/kvm/vcpu_onereg.c
arch/riscv/kvm/vcpu_sbi.c
arch/riscv/kvm/vcpu_sbi_replace.c