MIPS: add definitions for Loongson-specific CP0.Diag1 register
authorWANG Xuerui <git@xen0n.name>
Wed, 29 Jul 2020 13:14:16 +0000 (21:14 +0800)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 31 Jul 2020 15:52:29 +0000 (17:52 +0200)
commit2480c914699ecdf8b560f7af23b1a9c521084e04
tree73e23afb9bca97563ec9d0679fa5d79bd108c772
parentefd1b4ad3d5178a74387bc5ff69a2d4585f586c6
MIPS: add definitions for Loongson-specific CP0.Diag1 register

This 32-bit CP0 register is named GSCause in Loongson manuals. It carries
Loongson extended exception information. We name it Diag1 because we
fear the "GSCause" name might get changed in the future.

Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/include/asm/mipsregs.h